1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device capable of preventing voids from being created in a silicon substrate caused by oxide etchant penetrating into the silicon substrate.
2. Description of the Prior Art
Various kinds of silicon nitride layers (hereinafter, simply referred to as nitride layers) are used for manufacturing semiconductor devices. For example, when manufacturing a DRAM, a silicon oxide layer is formed as a buffer oxide layer through a CVD (chemical mechanical deposition) process after performing a gate etching process in order to improve device characteristics. After that, a nitride spacer in the form of a nitride layer is fabricated. Even though a space between gates becomes narrow, a spacer must be deposited with a thin thickness and a superior step-coverage characteristic while allowing gates to have insulation characteristics with respect to each other. Accordingly, the nitride layer is used for the spacer because the nitride layer has superior step-coverage and insulation characteristics as compared with an oxide layer.
In addition, the nitride spacer is used as a barrier when a dopant ion implantation process is carried out so as to improve junction and transistor characteristics. Moreover, the nitride spacer is used as a barrier when an etching process is carried out in order to prevent SAC fail between a gate and a bit line and between a gate and a capacitor, thereby improving reliability and a yield rate of semiconductor devices.
However, since the nitride spacer has inferior film quality, if a buffer oxide layer and a nitride spacer are sequentially formed after the gate etching process has been carried out, the nitride spacer does not sufficiently function as a barrier against oxide etchant when a wet dip process is carried out for an oxide spacer in the form of an oxide layer, so the buffer oxide layer may be partially etched. As a result, a silicon substrate, which is attacked by wet chemical when the dopant ion implantation process and the gate etching process are carried out, is damaged by oxide etchant. Accordingly, as shown in FIG. 1, a void having a depth above 1 μm is created in the silicon substrate.
Herein, the silicon substrate may be damaged because a silicon lattice is damaged due to high-energy ion implantation or due to dopants excessively distributed over the whole area of a surface of the silicon substrate when a surface channel is formed. In addition, after the silicon lattice damage has been created, a damage overlap may occur in the silicon substrate because the silicon substrate is further damaged by etchant when the gate etching process is carried out or the silicon substrate is locally weakened due to an attack of wet chemical after the gate etching process has been carried out.
The void created in the silicon substrate is exposed when a landing plug contact is formed so that polysilicon for a plug is deposited in the void. In this case, a junction to a gate, a well, and an electric circuit-short between bit lines may be caused, so that junction leakage current, which is fatal to the semiconductor device, is increased. As a result, row and column fail is created, deteriorating device characteristics and a yield rate of the semiconductor device.